1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to techniques for handling uncorrectable memory errors that reduce the impact of noise.
2. Description of Related Art
Present day memory subsystems include substantial error correction mechanisms. The error correction mechanisms make it possible to extend the size, increase the speed and/or reduce the power consumption of memory devices, while maintaining error-free operation via correction of correctable errors and via re-trying occasional uncorrectable errors that occur, i.e., those errors that exceed the capacity of the error-correcting code (ECC) that is employed for error checking and correction.
When uncorrectable errors occur, a typical response is to retry the memory access for which the error occurred, in the hope that the error was due to a transient condition that will not cause a memory error on the second attempt. However, retry of a memory access for which the error has an underlying cause increases the risk that a subsequent read to a different memory location error will also experience an error that will go undetected. Error correction algorithms have a very small but finite mis-correction rate in the presence of errors. Therefore, a subsequent error may not actually be corrected and produce an erroneous value.
Therefore, It would therefore be desirable to provide a memory controller that provides more reliable and robust operation, in particular when uncorrectable memory errors are detected that can be caused by transient noise events.